Senior/Staff Physical Design Engineer

Back to Search Results

Senior/Staff Physical Design Engineer

Apply

Save Job

Category

Chip Design

Location

Bangalore

Experience

More than 8 Years Work Expe.

Job Description

Lead Block Coordinator (APR / Physical Design) — 10+Yrs (Innovus)

• 10+ years of ASIC/SoC Physical Design / APR experience in a reputed product company, with multiple tapeouts.

• Senior Block Coordinator responsible for planning/execution and closure of 15+ blocks.

• Strong hands-on expertise in Cadence Innovus: floorplan, place/opt, CTS, route, and ECO closure at block level.

• Proven ability to drive timing closure (setup/hold), MMMC, constraints/exceptions alignment, and QoR improvement across blocks.

• Solid experience in congestion/routability debugging (macro placement/pin access/blockages/density) and driving closure actions with clear metrics.

• Experience across advanced and lower/mature nodes (e.g., 2/3/4/6nm).

• Strong understanding of block signoff readiness and coordination for DRC/LVS, SI-aware optimization, and IR/EM closure with signoff teams.

• Mandatory scripting/automation: strong Tcl (Innovus) for flow execution, report parsing, and QoR tracking; Python/Perl/Shell preferred.

• Strong cross-team coordination with STA/DFT/Synthesis/CAD.

Main Requirements and Qualifications

Lead Block Coordinator (APR / Physical Design) — 10+Yrs (Innovus)

Jobs Like This

Chip Design

RTL Design Lead

Save Job

More than 8 Years Work Expe.

Bangalore

Chip Design

Senior Verification Engineer

Save Job

More than 4 Years Work Expe.

Bangalore

Chip Design

DFT STA Lead

Save Job

More than 4 Years Work Expe.

Bangalore

Chip Design

DFT Engineer (Staff/Senior Staff Level)

Save Job

More than 4 Years Work Expe.

Bangalore

Chip Design

USB and System Level Verification Lead

Save Job

More than 8 Years Work Expe.

Bangalore

Chip Design

Design Verification Engineer- Display Interface Protocol Specialist

Save Job

More than 4 Years Work Expe.

Bangalore

See other jobs like this